Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/142908
Title: Low power optimization approaches for multiplier architecture
Researcher: Vijayakumar, S.
Guide(s): Korah, Reeba
Keywords: Architecture
Clock
Data
Pipelining
Power
University: Anna University
Completed Date: may, 2015
Abstract: Abstract available
Pagination: xviii, 163p.
URI: http://hdl.handle.net/10603/142908
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File41.09 kBAdobe PDFView/Open
02_certificate.pdf3.12 MBAdobe PDFView/Open
03_abstract.pdf24.7 kBAdobe PDFView/Open
04_acknowledgement.pdf835.49 kBAdobe PDFView/Open
05_table of contents.pdf28.34 kBAdobe PDFView/Open
06_list of tables.pdf27.96 kBAdobe PDFView/Open
07_list of figures.pdf29.12 kBAdobe PDFView/Open
08_list of symbols and abbreviations.pdf27.7 kBAdobe PDFView/Open
09_chapter 1.pdf48.39 kBAdobe PDFView/Open
10_chapter 2.pdf812.15 kBAdobe PDFView/Open
11_chapter 3.pdf303.56 kBAdobe PDFView/Open
12_chapter 4.pdf420.02 kBAdobe PDFView/Open
13_conclusion and future scope.pdf28.51 kBAdobe PDFView/Open
14_appendix 1.pdf28.03 kBAdobe PDFView/Open
15_appendix 2.pdf50.62 kBAdobe PDFView/Open
16_references.pdf65.43 kBAdobe PDFView/Open
17_list of publications.pdf27.73 kBAdobe PDFView/Open


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