Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/140201
Title: Architectural framework for low power variable length FFT processor
Researcher: Augusta Sophy Beulet, P.
Guide(s): Srinivasan, R.
Keywords: Fourier
Framework
Goals
Memory
Power
University: Anna University
Completed Date: october, 2015
Abstract: Abstract available
Pagination: xxii, 233p.
URI: http://hdl.handle.net/10603/140201
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File114.58 kBAdobe PDFView/Open
02_certificate.pdf571.08 kBAdobe PDFView/Open
03_abstract.pdf275.69 kBAdobe PDFView/Open
04_acknowledgement.pdf268.32 kBAdobe PDFView/Open
05_table of contents.pdf205.61 kBAdobe PDFView/Open
06_list of tables.pdf197.61 kBAdobe PDFView/Open
07_list of figures.pdf273.89 kBAdobe PDFView/Open
08_list of symbols and abbreviations.pdf282.81 kBAdobe PDFView/Open
09_chapter 1.pdf807.38 kBAdobe PDFView/Open
10_chapter 2.pdf1.09 MBAdobe PDFView/Open
11_chapter 3.pdf1.04 MBAdobe PDFView/Open
12_chapter 4.pdf1.29 MBAdobe PDFView/Open
13_chapter 5.pdf1.13 MBAdobe PDFView/Open
14_chapter 6.pdf1 MBAdobe PDFView/Open
15_results and conclusion.pdf956.15 kBAdobe PDFView/Open
16_appendix 1.pdf509.72 kBAdobe PDFView/Open
17_references.pdf449.13 kBAdobe PDFView/Open
18_list of publications.pdf275.63 kBAdobe PDFView/Open


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