Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/13799
Title: Area efficient reconfigurable resource sharing architecture for future wireless communications
Researcher: Suresh T
Guide(s): Shunmuganathan, K.L
Keywords: Reconfigurable resource sharing, architecture, wireless communications, Wide-bad Code Division Multiple Access(WCDMA), Orthogonal Frequency Division Multiplexing (OFDM), Wireless Local Area Network(WLAN), Wireless Fidelity(WiFi)
Upload Date: 9-Dec-2013
University: Anna University
Completed Date: 
Abstract: The fast developments in the field of wireless communication require more flexible and cost effective radio architecture. This architecture should have the capability to dynamically alter the functional blocks of physical layer to support different wireless communication technology standards. Therefore, there is a demand for the use of a basic architecture that can be reconfigured to support both existing and future wireless communication technology standards. Field Programmable Gate Array architectures (FPGAs) provide a suitable platform to achieve such dynamic reconfigurations. This thesis explores the use of FPGAs in the design of reconfigurable architecture. Using a case study, it is demonstrated that this architecture efficiently configures to support different modulation schemes for Wide-band Code Division Multiple Access (WCDMA) standard and Orthogonal Frequency Division Multiplexing (OFDM) based Wireless Local Area Network (WLAN), a.k.a Wireless Fidelity (WiFi). The most innovative part of this architecture is that it exploits multiplier-less algorithm and algorithmic strength reduction transformation technique to reduce large number of multipliers to achieve area efficiency. The thesis also proposes a method for mapping applications onto the reconfigurable resource sharing architecture. The similarities in computational processing elements of Fast Fourier Transform (FFT) in OFDM and RAKE receiver in WCDMA are identified and these elements are effectively reused in the hardware while reconfiguring to different standards. An area reduction of about 15-20 percent in the proposed FFT implementation and 90-91 percent in the proposed RAKE receiver is achieved compared to conventional architecture. This thesis demonstrates that the proposed architecture is used to provide flexibility, performance, efficiency and better resource utilization even while meeting the area and power constraints set by a particular design. newline newline newline
Pagination: xx, 118
URI: http://hdl.handle.net/10603/13799
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File49.56 kBAdobe PDFView/Open
02_certificates.pdf794.14 kBAdobe PDFView/Open
03_abstract.pdf13.83 kBAdobe PDFView/Open
04_acknowledgement.pdf15.27 kBAdobe PDFView/Open
05_contents.pdf40.6 kBAdobe PDFView/Open
06_chapter 1.pdf246.21 kBAdobe PDFView/Open
07_chapter 2.pdf711.11 kBAdobe PDFView/Open
08_chapter 3.pdf300.94 kBAdobe PDFView/Open
09_chapter 4.pdf55.47 kBAdobe PDFView/Open
10_chapter 5.pdf447.46 kBAdobe PDFView/Open
11_chapter 6.pdf139 kBAdobe PDFView/Open
12_chapter 7.pdf17.52 kBAdobe PDFView/Open
13_references.pdf42.8 kBAdobe PDFView/Open
14_publications.pdf14.04 kBAdobe PDFView/Open
15_vitae.pdf12.77 kBAdobe PDFView/Open


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