Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/13653
Title: Investigations on techniques for power reduction and failure detection in SRAM
Researcher: Sivamangai N M
Guide(s): Gunavathi, K.
Keywords: Power reduction, failure detection, Static Random Access Memory, Adaptive Body Bias, Reverse Body Bias
Upload Date: 5-Dec-2013
University: Anna University
Completed Date: 
Abstract: With each new CMOS technology generation, the functional correctness of the design and design parameters become more sensitive to the increasing subthreshold leakage current and circuit parametric variations. These variations in process parameters severely affect the minimum geometry transistors commonly used in area constrained circuits such as Static Random Access Memory (SRAM) cells. Stored SRAM cell data faces the following failure mechanisms. Parametric failures like read upset, access time failure, hold failure and write failure due to process parameter variations. Soft errors due to cosmic particles or alpha particles from die packaging. Variations in the process parameter results in functional failures such as read, write, access and hold failures in SRAM. If the variations in process parameters, in particular threshold voltage are prevented, then the probability of occurrence of functional failures can be avoided. Hence a self repairable architecture capable of identifying the SRAM array with low and high Vt transistors by monitoring the leakage current of the SRAM array is proposed. It utilizes Adaptive Body Bias (ABB) technique, as an adaptive repair technique. By applying Reverse Body Bias (RBB) to low Vt transistors, their Vt increases thereby reducing read and hold failures in SRAM cells. The result shows that the proposed architecture is able to reduce the amount of deviation of high Vt values from nominal Vt values as compared to existing technique. This results in a highly reliable self repairable architecture as compared to the existing architectures. This voltage pulse is fed to the asynchronous latch that generates the error signal. To enable the BICS operation under operating condition of SRAM, the logic circuitry with delay element is used. This circuit is used to control the reset signal for all operating conditions. The result shows that the proposed BICS is capable of detecting soft errors both at standby and operating modes. newline newline newline
Pagination: xxvii, 165
URI: http://hdl.handle.net/10603/13653
Appears in Departments:Faculty of Information and Communication Engineering

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02_certificates.pdf894.15 kBAdobe PDFView/Open
03_abstract.pdf26.09 kBAdobe PDFView/Open
04_acknowledgement.pdf14.22 kBAdobe PDFView/Open
05_contents.pdf54.12 kBAdobe PDFView/Open
06_chapter 1.pdf51.69 kBAdobe PDFView/Open
07_chapter 2.pdf242.66 kBAdobe PDFView/Open
08_chapter 3.pdf360.03 kBAdobe PDFView/Open
09_chapter 4.pdf206.46 kBAdobe PDFView/Open
10_chapter 5.pdf798.15 kBAdobe PDFView/Open
11_chapter 6.pdf122.87 kBAdobe PDFView/Open
12_chapter 7.pdf459.27 kBAdobe PDFView/Open
13_chapter 8.pdf26.03 kBAdobe PDFView/Open
14_references.pdf33.81 kBAdobe PDFView/Open
15_publications.pdf19.21 kBAdobe PDFView/Open
16_vitae.pdf13.38 kBAdobe PDFView/Open


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