Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/13423
Title: Certain investigations on power optimization techniques for data path cells in DSP blocks
Researcher: Marimuthu, C.N.
Guide(s): Thangaraj, P.
Keywords: Power optimization techniques, data path cells, DSP blocks, algorithm, transistor
Upload Date: 28-Nov-2013
University: Anna University
Completed Date: 
Abstract: Multiplier is one of the key hardware blocks in most of the digital and high speed systems such as FIR filters, Digital Signal Processors and Microprocessors. In fact the overall speed, area and power consumption of digital systems depend on Multipliers, being complex units. Multiplication in digital systems exhibits a variety of requirements for speed, area, power consumption and other specifications. In this thesis, various power reduction techniques for multipliers have been used at the algorithm (Macro) and transistor (Micro) level of abstraction. At the algorithm level, a low power parallel multiplier has been designed by equipping Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit. Further, in the same level of abstraction, various multiplier architectures are compared in terms of dissipated energy, propagation delay and area occupation in view of low power and low voltage signal processing for low frequency applications. Finally at transistor level of abstraction, the low power adder cells the basic building blocks of Multiplier have been designed with various transistor counts and compared with conventional adders. The analysis showed that the 10T full adder was more suitable for low power applications as a Multiplier. Since the existing Static Energy Recovery Full adder (SERF) within the 10T full adder has constrains such as more glitches and low threshold voltage, the new Gate Diffusion Input (GDI) full adder has been proposed in order to design a Low Power Array Multiplier. These parametric analyses had been carried out using Tanner CAD tool, with varying supply voltage values. While designing the Low Power Multiplier, the Power Delay Product (PDP) has been taken into account both at the abstraction level of algorithm and transistor. The investigation helps to choose proper choice of appropriate Multipliers and Adders in different digital applications, according to the requirements. newline newline newline
Pagination: xviii, 115
URI: http://hdl.handle.net/10603/13423
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File49.68 kBAdobe PDFView/Open
02_certificates.pdf959.83 kBAdobe PDFView/Open
03_abstract.pdf16.23 kBAdobe PDFView/Open
04_acknowledgement.pdf13.06 kBAdobe PDFView/Open
05_contents.pdf45.78 kBAdobe PDFView/Open
06_chapter 1.pdf45.15 kBAdobe PDFView/Open
07_chapter 2.pdf102.04 kBAdobe PDFView/Open
08_chapter 3.pdf729.33 kBAdobe PDFView/Open
09_chapter 4.pdf292.1 kBAdobe PDFView/Open
10_chapter 5.pdf283.79 kBAdobe PDFView/Open
11_chapter 6.pdf175.43 kBAdobe PDFView/Open
12_chapter 7.pdf17.19 kBAdobe PDFView/Open
13_references.pdf28.27 kBAdobe PDFView/Open
14_publications.pdf16.36 kBAdobe PDFView/Open
15_vitae.pdf10.9 kBAdobe PDFView/Open


Items in Shodhganga are protected by copyright, with all rights reserved, unless otherwise indicated.