Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/13051
Title: Certain investigations Into Optimization of multi loop problems for reconfigurable VLSI Design
Researcher: Sundari, B. Bala Tripura
Guide(s): Sundaram, G A Shanmugha
Keywords: Multi-level nested loop algorithms;
Precedence constraints
n-D problem space
High level synthesis
Upload Date: 20-Nov-2013
University: Amrita Vishwa Vidyapeetham (University)
Completed Date: 2013
Abstract: The high integration density of very large scale integrated (VLSI) circuits has made system on chip design (SoC) become a reality. With increasing complexity of SoC, it becomes important to raise the design abstraction to a behavioral level in order to enable the development of new design methodologies to tap the full potential of reconfigurable SoC platforms for various compute bound applications. The focus here is on mapping of computationally intensive multi-loop nest algorithms (termed as n-dimensional) onto parallel array architectures where the target architecture considered is a systolic array comprising of locally interconnected grid of processing elements (PEs). The problem of determining the configuration of PE array for mapping of the n-dimensional (n-D) nested loop problems has been receiving considerable attention in the recent years. The mapping methodologies, which have been used in systolic array design, use the set of dependencies in the n-D nested loop problems represented by dependence vectors (DV) and determine the projection matrix constituted of the processor space matrix (P) and the timing function or vector (S). Heuristic approaches have been used to search for the projection matrices, but the complexity of search procedure grows with the loop nest size and hence these methods need a large computational effort. The mapping methodology proposed in this thesis identifies that for multidimensional problems, the compute sub-space lies strictly in a lower dimension. The computational expression and the subspace in which it lies are defined as the computational trail vector (CTV) and (n-x)-D compute sub-space respectively. The PE array is allocated to each point in this subspace.
Pagination: xxi, 225p.
URI: http://hdl.handle.net/10603/13051
Appears in Departments:Department of Electronics & Communication Engineering (Amrita School of Engineering)

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File223.23 kBAdobe PDFView/Open
02_certificate.pdf299.73 kBAdobe PDFView/Open
03_declaration.pdf273.93 kBAdobe PDFView/Open
04_acknowledgements.pdf108.97 kBAdobe PDFView/Open
05_abstract.pdf243.54 kBAdobe PDFView/Open
06_dedication.pdf113.7 kBAdobe PDFView/Open
07_contents.pdf811.57 kBAdobe PDFView/Open
08_glossary.pdf501.6 kBAdobe PDFView/Open
09_list of listing.pdf118.4 kBAdobe PDFView/Open
10_list of tables.pdf116.36 kBAdobe PDFView/Open
11_synopsis.pdf666.96 kBAdobe PDFView/Open
12_chapter 1.pdf413.65 kBAdobe PDFView/Open
13_chapter 2.pdf936.59 kBAdobe PDFView/Open
14_chapter 3.pdf623.33 kBAdobe PDFView/Open
15_chapter 4.pdf1.01 MBAdobe PDFView/Open
16_chapter 5.pdf1.37 MBAdobe PDFView/Open
17_chapter 6.pdf894.33 kBAdobe PDFView/Open
18_chapter 7.pdf310.42 kBAdobe PDFView/Open
19_reference.pdf3.88 MBAdobe PDFView/Open


Items in Shodhganga are protected by copyright, with all rights reserved, unless otherwise indicated.