Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/123622
Title: Parallel Multipliers Architectural Exploration and Designing
Researcher: SUBHENDU KUMAR SAHOO
Guide(s): CHANDRA SHEKHAR
Keywords: Parallel Multipliers, Architectural Exploration
University: Birla Institute of Technology and Science
Completed Date: 
Abstract: Multiplication is one of the basic arithmetic operations used in almost all newlinecomputations. The performance of many computational units is dominated by the speed at newlinewhich a multiplication operation can be executed. Taking this into consideration various newlineresearchers have developed novel algorithms and circuit techniques for multiplication to newlineprovide higher speeds and optimized use of silicon area. newlineThis thesis explores different algorithms, architectures and circuit techniques used for newlineparallel multiplier implementations. In this process ten architectures are defined. Each newlinearchitecture is used to design multipliers of operand sizes 8, 16, 32, 54 and 64 bits. For each newlinemultiplier delay is calculated in terms of the delay of two-input XOR gate. All multipliers are newlinesynthesized using Magma EDA tool. Post synthesis delay, power, area and cell counts are newlinefound. Based on these results, best architecture for a multiplier of required operand size and newlinepreferred figure of merit is determined. newlineIn the process of exploration of circuit techniques, a new Booth encoder and a new newlineBooth selector circuit are proposed for partial product generation. These two circuits for newlinepartial product generation are smaller in transistor count and are comparable to the bestreported newlinecircuits in terms of delay and power consumption. A new 4:2 compressor circuit is newlinealso proposed, which outperforms other recently reported 4:2 compressors in terms of energy newlinedelay product and transistor count. newlineA novel final adder architecture named as CLEBC is proposed based on redundant newlinebinary arithmetic, equivalent bit conversion algorithm and carry-lookahead technique. This newlineadder is faster than the carry-lookahead adder for any bit length. For addition of two 32-bit newlinenumbers, a CLEBC adder is 30% faster than a carry-lookahead adder.
Pagination: 3.54 MB
URI: http://hdl.handle.net/10603/123622
Appears in Departments:Electrical & Electronics Engineering

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