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Title: Design of robust sub-threshold circuits for ultra low power moderate throughput applications
Researcher: Pable, Sachin Dattatray
Guide(s): Mohd. Hasan
Keywords: Electronics Engineering
Technology Scaling
Deep Nanometer Era
Power Consumption
Routing Switch Box Design
Global Interconnects
Upload Date: 19-Sep-2013
University: Aligarh Muslim University
Completed Date: 2012
Abstract: There are two sources of power consumption in CMOS namely dynamic and leakage. The dynamic power in CMOS is a quadratic function of the supply voltage and the leakage power is its exponential function. Hence, the most effective way to reduce the power consumption is through supply voltage scaling. The extreme case of supply voltage scaling is the subthreshold regime in which it is scaled below the threshold voltage to achieve ULP. The leakage current is used as a driving current in subthreshold circuits and therefore, the speed degrades considerably. The design of ULP digital circuits has received widespread attention due to the rapid growth of ULP applications like body sensor networks and implantable medical electronics etc. Despite the speed degradation, few researchers have tried to improve the speed under subthreshold conditions. This thesis presents innovative techniques to enhance the speed and robustness of subthreshold circuits with a limited power budget to widen their application domain. There is a significant market for ULP applications which is currently being dominated by ASIC. The cost of ASIC is exponentially rising due to high NRE cost. Hence, it is important to extend the domain of FPGA even under subthreshold conditions so that they can also be employed for reconfigurable ULP applications in place of the expensive and more rigid ASICs in future technologies. This thesis proposes a low power FPGA routing switch box that utilizes the leakage current for body biasing. This technique significantly enhances speed, lowers switching energy, and increases robustness. The device optimized for superthreshold circuits may not provide the optimum subthreshold performance. Hence, FPGA interconnect resources performance has been enhanced using newlinedevice optimisation techniques under subthreshold conditions. The interconnect primarily determines the performance of systems at the nanoscale. Hence, the design of interconnect is crucial in improving the performance under subthreshold conditions.
Pagination: xx, 208p.
Appears in Departments:Department of Electronics Engineering

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01_title.pdfAttached File33.29 kBAdobe PDFView/Open
02_certificate.pdf130.48 kBAdobe PDFView/Open
03_acknowledgement.pdf28.42 kBAdobe PDFView/Open
04_table of contents.pdf37.58 kBAdobe PDFView/Open
05_abstract.pdf30.77 kBAdobe PDFView/Open
06_list of tables.pdf27.12 kBAdobe PDFView/Open
07_list of figures.pdf120.15 kBAdobe PDFView/Open
08_list of symbols.pdf121.9 kBAdobe PDFView/Open
09_list of abberivations.pdf31.58 kBAdobe PDFView/Open
10_list of publications.pdf66.22 kBAdobe PDFView/Open
11_chapter 1.pdf99.89 kBAdobe PDFView/Open
12_chapter 2.pdf412.86 kBAdobe PDFView/Open
13_chapter 3.pdf327.46 kBAdobe PDFView/Open
14_chapter 4.pdf420.68 kBAdobe PDFView/Open
15_chapter 5.pdf491.41 kBAdobe PDFView/Open
16_chapter 6.pdf857.33 kBAdobe PDFView/Open
17_chapter 7.pdf350.11 kBAdobe PDFView/Open
18_chapter 8.pdf509.43 kBAdobe PDFView/Open
19_chapter 9.pdf192.38 kBAdobe PDFView/Open
20_references.pdf138.53 kBAdobe PDFView/Open

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