Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/144731
Title: Compiler assisted parallelization and optimization for multicore architecture
Researcher: Kiran, D. C.
Guide(s): Gurunarayanan, S
Keywords: Compiler, Parallelization, Optimization, Architecture
University: Birla Institute of Technology and Science
Completed Date: 1/8/2014
Abstract: Compiler Assisted Parallelization and Optimization for Multicore Architecture newlineContinuous improvement of VLSI technology coupled with need for faster processing capability has led to several innovations in the field of computer architecture resulting in development of multicore processors. A multicore processor has multiple processor cores on a single chip. Each individual core has separate register file and is capable of executing complete ISA (Instruction Set Architecture). In order to exploit the computing capabilities of multicore processors, significant amount of research in the area of code parallelization and multiprocessing has been carried out. An application running on a multicore system does not guarantee the performance improvement until the application has been explicitly designed to take advantage of multicore processor. To develop an application that exploits computing capabilities of multicore, two approaches are followed. The first approach is to develop an explicitly parallel code that can be scheduled on multiple cores of a given processor and the other approach is using a compiler to extract fine grained parallelism by identifying the sets of instructions that can be executed in parallel. Current focus by researcher and programming language developers is to exploit coarse grain thread and data-level parallelism. There is very little effort from the research community toward the exploitation of compiler driven fine grained parallelism of a sequential program. newlineThe multicore processors can be made to exploit fine grained parallelism of a given code by exposing the low level architectural details to the compiler and operating systems. Several multicore architectures are proposed and are being designed such that it supports the minimal set of operations required for executing an instruction, and other tasks including extracting the fine grained parallelism are left for compilers and run time environment. The runtime environment can manage resource allocation, extracting newlinevii newlineparallel constructs for d
Pagination: XV
URI: http://hdl.handle.net/10603/144731
Appears in Departments:Electrical & Electronics Engineering

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