Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/123771
Title: quotEnergy Efficient Techniques for Multi tasking Embedded Systems Cache Design and Task Scheduling Algorithms
Researcher: BIJU K R
Guide(s): S Gurunarayanan
Keywords: Embedded System, Cache Design
University: Birla Institute of Technology and Science
Completed Date: 
Abstract: In most Real-Time Embedded Systems, the limited battery life is a major cause of newlineinterest and concern. In a bid to optimize the energy consumption, this issue is newlineaddressed at various levels Architecture level (memory subsystem, Dynamic newlineVoltage Scaling / Dynamic Frequency Scaling), Systems level (process management, newlinememory management and compiler techniques), and Application level (efficient data newlinestructures and algorithm design). Of the various components, the memory subsystem newline(architecture level) and the operating system-related activities (systems level) share a newlineconsiderable proportion of the energy consumption by Embedded Systems. newlineThis thesis addresses the issue of optimizing energy consumption in Embedded newlineSystem at the Architecture and the Systems levels. The primary source of energy newlineconsumption at the architecture level is the memory subsystem, especially the cache newlinememory architecture. This work presents various techniques to reduce this cacherelated newlineenergy consumption, majority of which is attributed to the data movement newlineacross the memory hierarchy demanded and initiated by cache misses. One way to newlinereduce this energy consumption is to improve the cache performance which entails an newlineenhanced cache hit rate. This work proposes a new replacement policy called Late newlineLeast Recently Used (LLRU) replacement policy which while deciding on newlinereplacement, particularly considers cache lines that are shared among processes. newlineDifferent hardware designs and implementations of the LRU and LLRU replacement newlinepolicy have been put forth. Here, a way predictive placement scheme, a newlinemodification of the way predictive cache, for reducing the cache access time and newlinepower consumption has also been proposed and evaluated. One other means of newlineachieving reduced energy consumption in Embedded Systems cache is to power newlinedown all the unused data and tag ways. Motivated by this reasoning, this work newlineproposes two process aware cache architectures, the Process Aware Selective newlinePlacement (PASP) and the Shared Memory Process Aware Selective Place
Pagination: 1.68 MB
URI: http://hdl.handle.net/10603/123771
Appears in Departments:Computer Science & Information Systems

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