Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/102429
Title: Low Power Testing Techniques for VLSI Modules
Researcher: Balwinder Singh
Guide(s): Narang, Sukhleen Bindra
Keywords: Low Power Testing Techniques
VLSI Modules
University: Guru Nanak Dev University
Completed Date: 04/10/2013
Abstract: newline Available
Pagination: 28cm
URI: http://hdl.handle.net/10603/102429
Appears in Departments:Department of Electronics Technology

Files in This Item:
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01_title.pdfAttached File62.02 kBAdobe PDFView/Open
02_certificate.pdf20.76 kBAdobe PDFView/Open
03_declaration.pdf17.47 kBAdobe PDFView/Open
04_acknowledgements.pdf24.77 kBAdobe PDFView/Open
05_abstract.pdf30.85 kBAdobe PDFView/Open
06_contents.pdf28.54 kBAdobe PDFView/Open
07_list of figures.pdf26.3 kBAdobe PDFView/Open
08_list of tables.pdf20.62 kBAdobe PDFView/Open
09_abbreviations.pdf20.84 kBAdobe PDFView/Open
10_thesis outcomes.pdf26.9 kBAdobe PDFView/Open
11_chapter 1.pdf452.32 kBAdobe PDFView/Open
12_chapter 2.pdf251.83 kBAdobe PDFView/Open
13_chapter 3.pdf2.68 MBAdobe PDFView/Open
14_chapter 4.pdf4.85 MBAdobe PDFView/Open
15_chapter 5.pdf874.86 kBAdobe PDFView/Open
16_chapter 6.pdf36.13 kBAdobe PDFView/Open
17_references.pdf97.3 kBAdobe PDFView/Open


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